Abstract:
Formal verification of variant requirements has gained much interest in the software
product line (SPL) community. Feature diagrams are widely used to model product line
variants. However, there is a lack of precisely defined formal notation for representing
and verifying such models. This report presents an approach to analyzing SPL variant
feature diagrams using first-order logic. The logical representation provides a precise and
rigorous formal interpretation of the feature diagrams. Logical expressions can be built
by modeling variants and their dependencies by using propositional connectives. These
expressions can then be validated by any suitable verification tool such as Alloy. A case
study of a Computer Aided Dispatch (CAD) system variant feature model is presented to
illustrate the analysis and verification process.
Description:
This thesis submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Computer Science and Engineering of East West University, Dhaka, Bangladesh