Abstract:
A simple gateway capacitance- voltage model for MOS devices with semi-classical method proposed. Quintana mechanical QM effects are neglected in the model. In this model effect of interface trap charges are included. The model is valid for arbitrary distribution of Du with in the silicon energy band gap. We have performed numerical calculation for uniform carbolic dit profile. The interface trap charges are included in surface charges to calculate the outside electrical field and this oxide electrical field field is used to calculate the gate voltage.
Description:
This thesis submitted in partial fulfillment of the requirements for the degree of B.Sc in Electrical and Electronic Engineering of East West University, Dhaka, Bangladesh.
