Effects of Interface states on MOS Gate C-V Characteristics

dc.contributor.author	Shams, Md. Makhdum Elahi Mashravi
dc.contributor.author	Shawon, Mehrab Jamil
dc.contributor.author	Baidya, Suprava
dc.date.accessioned	2017-02-14T05:07:34Z
dc.date.available	2017-02-14T05:07:34Z
dc.date.issued	8/31/2009
dc.identifier.uri	http://dspace.ewubd.edu/handle/2525/2060
dc.description	This thesis submitted in partial fulfillment of the requirements for the degree of B.Sc in Electrical and Electronic Engineering of East West University, Dhaka, Bangladesh.	en_US
dc.description.abstract	A simple gateway capacitance- voltage model for MOS devices with semi-classical method proposed. Quintana mechanical QM effects are neglected in the model. In this model effect of interface trap charges are included. The model is valid for arbitrary distribution of Du with in the silicon energy band gap. We have performed numerical calculation for uniform carbolic dit profile. The interface trap charges are included in surface charges to calculate the outside electrical field and this oxide electrical field field is used to calculate the gate voltage.	en_US
dc.language.iso	en_US	en_US
dc.publisher	East West University	en_US
dc.relation.ispartofseries	;EEE00004
dc.subject	MOS Gate C-V Characteristics	en_US
dc.title	Effects of Interface states on MOS Gate C-V Characteristics	en_US
dc.type	Thesis	en_US