Abstract:
The scaling down of devices has been the driving force in the advancement of technology since the beginning of 19th century. 65 nm technologies become conventional in 2006 and 45 nm technology was announced in 2007. But further scaling down is facing some serious limitations. These limitations are related to fabrication technology and device performances. In this work, we have implemented in ADS a 6-capacitor compact model of a carbon nanotube transistor proposed by J. Deng and H.-S P. Wong. The model includes phonon scattering and band to band tunneling current. The code is written in Verilog-A and it is linked to ADS by a transistor symbol of 4-terminals. The code is verified by simulating the I-V characteristics of nchannel
and p-channel CNFETs.
Description:
This thesis submitted in partial fulfillment of the requirements for the degree of B.Sc in Electrical and Electronic Engineering of East West University, Dhaka, Bangladesh.
