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An Efficient Fault Tolerant Design of Reversible Sequential Circuits

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dc.contributor.author Tanzil, H.M.
dc.contributor.author Hasan, Maksudul
dc.contributor.author Jahan, Imtiaz
dc.date.accessioned 2016-11-24T05:36:46Z
dc.date.available 2016-11-24T05:36:46Z
dc.date.issued 9/12/2015
dc.identifier.uri http://dspace.ewubd.edu/handle/2525/1961
dc.description This thesis submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Computer Science and Engineering of East West University, Dhaka, Bangladesh. en_US
dc.description.abstract In this paper we proposed reversible synthesis for the several popular sequential circuits such as shift register, binary adder and Multipliers. All the proposed circuits are constructed with the parity preserving reversible gates. Thus, the proposed circuits inherently become fault tolerant. In addition, several lower bounds on the number of garbage outputs and constant inputs of the reversible fault tolerant sequential circuits have been proposed. It has also been shown that the proposed circuits are constructed with these optimal parameters. Moreover, the generalized algorithms for the fault tolerant sequential circuits have been presented. The performance study shows that the proposed fault tolerant circuits are much faster than the existing reversible non-fault tolerant counterparts. en_US
dc.language.iso en_US en_US
dc.publisher East West University en_US
dc.relation.ispartofseries ;CSE00040
dc.subject Design of Reversible Sequential Circuits en_US
dc.title An Efficient Fault Tolerant Design of Reversible Sequential Circuits en_US
dc.type Thesis en_US


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