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An Optimal Design of Reversible Fault Tolerant n Bit Comparator

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dc.contributor.author Ahmed, Istiaq
dc.contributor.author Trisha, Nusrat Jahan
dc.date.accessioned 2016-11-24T05:37:06Z
dc.date.available 2016-11-24T05:37:06Z
dc.date.issued 9/10/2015
dc.identifier.uri http://dspace.ewubd.edu/handle/2525/1966
dc.description This thesis submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Computer Science and Engineering of East West University, Dhaka, Bangladesh. en_US
dc.description.abstract This thesis presents synthesis of the reversible comparator. The proposed circuits are designed using only parity preserving Fredkin and Feynman double gates. Thus, these circuits inherently turn into fault tolerant circuits. In addition, a lower bound on the number of constant inputs and garbage outputs for the reversible fault tolerant comparator has been proposed. It has been evidenced that the proposed circuit is constructed with these optimal garbage outputs and constant inputs. Moreover, a design algorithm for the generalized fault tolerant comparator has been presented. The comparative results show that the proposed design performs much better and has significantly better scalability than the existing approaches. en_US
dc.language.iso en_US en_US
dc.publisher East West University en_US
dc.relation.ispartofseries ;CSE00043
dc.subject parity preserving Fredkin and Feynman double gates. en_US
dc.title An Optimal Design of Reversible Fault Tolerant n Bit Comparator en_US
dc.type Thesis en_US


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