Abstract:
As current travels all the way from the power supply to the silicon, it sees the current
path in each of the levels as resistive and inductive drops, thus voltage deteriorates.
Power droop in the silicon is a major cause for system performance degradation.
Higher frequency of operation and reduced power levels are limiting the timing and
voltage budget, which is designed in circuits to account for system noise, which
includes voltage drooping due to inductive losses. Novel techniques are evolved to
compensate for these losses at all levels, starting from motherboard, package, socket
and finally down to the silicon level.
Due to lack of available space, design constraints and fabrication difficulties,
decoupling at the die level is very limited. Though available decoupling techniques
exist for the board, package and socket, yet their response time is slow and in some
cases worthless.
Here a proposal is made to provide for decoupling at the CMOS levels, right where the
power is needed. This work merges the advanced DRAM technologies with that of
CMOS to create decoupling in silicon without taking any extra rooms for it. Simulation
of sub 100 run multi-metal layer circuit demonstrates the advantage of proposed
localized decoupling.
-ment
Description:
This thesis submitted in partial fulfillment of the requirements for the degree of B.Sc in Electrical and Electronic Engineering of East West University, Dhaka, Bangladesh.
