An Investigation on the Corner Effects of Non-classical MOS Architecture

Abstract

Traditionally, the technological development has been performed by means of the scaling down of the device dimensions, each vertically and laterally. Nonetheless, as device dimensions moved into nanometer regime, quantum mechanical tunnelling and bodily barrier have rendered device down-scaling a difficult task. Revolutionary measures, together with making use of substitute materials and replacement device structure are as a result inevitable to be able to maintain Moore‟s regulation. Among these novel devices, the vertical MOS transistor is deemed promising as it presents related, if now not better performance than different novel devices and yet it's CMOS method compatible. On this thesis, the effects of corner in the vertical MOS transistor had been investigated utilising 3-dimensional device simulator, ATLAS3D from Silvaco TCAD bundle. Various gate structure and gate widths were simulated and investigated. The gate length, LG was once stored at 60 nm for the entire simulations, with the gate oxide of 2nm thick and pillar measurement of 100nm × 100nm × 100nm. The substrate doping concentration used is 1×1018 cm-3, even as the source or drain area is modelled with abrupt junction and uniform concentration of 1×1021 cm-3. A evenly doped area of 1×1018 cm-3 is used to modelled a doubly doped drain constitution The simulation of the quadruple gate and corner gate vertical MOS transistor are also awarded and analyzed for width edge and corner effects. The current drive increases because the gate width is extended however off-state current decreases at identical time. This leads to lower subthreshold slope for higher gate dimension devices and could be thanks to additional distance of adjacent gates once the gate dimension is reduced, thus amplifying the dimension edge result. For many of the gate structures simulated, the corners of the pillar area unit determined to activate sooner than the non- corner sections, thus confirmed a threshold voltage decreasing at the corners. The corner section has shown a major contribution to complete drain current when the device is biased above the threshold voltage. With corner section occupying 240nm of the gate width, and the non-corner section taking 240nm, at 0.1V the drain current contribution of corner section is estimated to be 36.75% and at 1.0V the drain current contribution of corner section is estimated to be 2.30% founded on physical ratio. With corner section occupying 160nm of the gate width, and the non-corner section taking 160nm, at 0.1V the drain current contribution of corner section is estimated to be 85.43% and at 1.0V the drain current contribution of corner section is estimated to be 3.46% founded on physical ratio. In corner gate and double gate taking 80nm at 0.1V the drain current contribution of corner section is estimated to be 97.44% and at 1.0V the drain current contribution of corner section is estimated to be 6.20% founded on physical ratio. This is believed to be valuable to increase the saturation current drive. The percentage contribution of complete drain current from the corner section lowered when VG is decreased, and was once least at VG close to threshold voltage. However, when VG is further decreased, the corner begins to make contributions to the drain current once more and might overtake the have an effect on of non-corner section when the drain voltage is high. The discussion given during this thesis is intuitive and more verification with measured knowledge will certainly create it additional credible.