Performance Analysis of SI Nanowire Transistors Using Top of the Barrier Quantum Model

dc.contributor.author	Sakib, MD. Nazmus
dc.contributor.author	Jahan, Akther
dc.contributor.author	Karim, Fazlul
dc.date.accessioned	2023-04-09T05:02:47Z
dc.date.available	2023-04-09T05:02:47Z
dc.date.issued	2010-05-23
dc.identifier.uri	http://dspace.ewubd.edu:8080/handle/123456789/3964
dc.description	This thesis submitted in partial fulfillment of the requirements for the degree of B.Sc in Electrical and Electronic Engineering of East West University, Dhaka, Bangladesh.	en_US
dc.description.abstract	After more than 30 years of validation of Moore's law, the CMOS technology has already entered the nonoscale (sub-lOOnm) regime and faced strong limitations. The nanowire transistor is one of the candidates which have the potential; overcome the problems caused by shorts channel effect in SOI (silicon on insulator) MOSFETs.	en_US
dc.language.iso	en_US	en_US
dc.publisher	East West University	en_US
dc.relation.ispartofseries	;EEE00022
dc.subject	SI nanowire transistors, Barrier Quantum Model	en_US
dc.title	Performance Analysis of SI Nanowire Transistors Using Top of the Barrier Quantum Model	en_US
dc.type	Thesis	en_US