Process Simulation of FILOX Vertical MOSFET to Estimate Fabrication Parameters

Abstract

The aim of this thesis work is to study the Process simulation of FILOX vertical MOSFET to estimate fabrication parameters for RF application. Double gate or surround-gate vertical metal oxide semiconductor field effect transistors is delayed by the parasitic overlap capacitance related with their layout, which is larger than for a lateral MOSFET on the same technology node. A simple self-aligned process has been developed to reduce the parasitic overlap capacitance in vertical MOSFETs using nitride spacers on the sidewalls of the trench or pillar and a local oxidation. In this thesis we describe different steps of FILOX vertical MOSFET fabrication and finally we get 115nm of channel length , 140nm of junction depth, 3.3nm of gate oxide thickness, 4×1018 cm-3 of body doping and 2×1020 cm-3 of source/drain doping in the FILOX vertical MOSFET. We also describe the parameters that required to be changed to obtain different desired body doping value for our FILOX vertical MOSFET. This thesis we observed that decrease in dose of p-type implantation causes a decrease in body doping but this also changes the channel length. Therefore, to obtain our targeted channel length 115nm and junction depth 140nm we have to decrease the energy too. Simultaneously, we slightly need to decrease the dose and energy of n-type implantation. To get the desired body doping we see the alteration of channel length 115nm and junction depth 140nm. Then we adjusted the dose and energy of FILOX vertical MOSFET.